The present invention relates to the field of integrated circuit technology. More specifically an embodiment of the present invention relates to a synthesizable programmable logic architecture.
A relatively short life span of any particular integrated circuit design and competitive nature of electronic industry requires a short xe2x80x9ctime to marketxe2x80x9d period. Furthermore, the ever increasing complexity of integrated circuit (IC) devices mandates a departure from traditional time consuming xe2x80x9cpaper-and-pencilxe2x80x9d method of design to a more efficient method of xe2x80x9cdescribe-and-synthesizexe2x80x9d approach. Hardware Description Languages (HDLs) and computer aided design systems have been used throughout the industry to facilitate the design of integrated circuits and to shorten the time period in the design phase of the integrated circuit devices. Aided by HDLs, a designer describes the behavior or the structure of a digital circuit in HDL and a CAD system, in return, synthesizes the behavior and provides the designer with a schematic of the desired circuit in, a shortened period of time.
Ideally the consumer of ICs would prefer to have a general purpose chip such as a Universal Serial Bus (USB) controller to provide the ability to connect to many diverse interfaces such as disk drive, wireless systems, and modems. A response to such demand can take either of the two solutions: a) providing multiple pre-built logic blocks and allowing the designer to select between the logic blocks or b) providing a general purpose state machine-based logic block such as General programmable Interface (GPIF).
It is very difficult, even with highly programmable units such as GPIF, to anticipate all logic configurations required by future designs that utilize the general-purpose chip. Therefore a small amount of customization by the user is often required to convert and tailor interface signals between chips.
A well-known solution for implementing user customizable logic is the use of a programmable logic chip, e.g., a Complex Programmable Logic Device (CPLD) or Field Programmable Gate Array (FPGA) architecture. Incorporating a small programmable logic block onto a general-purpose chip such as USB controller would be a highly advantageous method for providing the user with the logic programming required for customization. However, CPLD technology is not, generally amenable to synthesis using standard logic design flows or incorporation into standard libraries, which can be employed by various chip geometries and technologies. Because conventional CPLDs are built using highly customized layouts and are fine-tuned to specific geometries and technologies, they are not suitable for synthesis in various standard digital technologies.
Devices such as FPGAs or CPLDs are gaining popularity in use, but components used in the design of these devices are not amenable to standard design libraries (e.g., memories, fuses, interconnects or routing matrices). To further improve the process of synthesizing a user programmable digital device, designers need tools to describe a complex electronic circuit and those devices, which are not amenable to a standard library, in a programmable logic language.
Therefore, a need exists to provide IC designers with tools to synthesize a complex programmable block using standard cell libraries. Another need exists to list all components used to design an electronic device in a standard design library using components, which are describable in HDL. Another need exists to build programmable logic blocks, which are synthesizable and do not use fuses, standard interconnect or routing matrices which are not amenable to a design library. Another need exists to design electronic devices, which are fast and consume less power.
The present invention provides a novel solution to these requirements.
Accordingly, an embodiment of the present invention provides IC designers with tools to synthesize a complex programmable logic device from a standard cell library. Another embodiment of the present invention provides substitutes for components which are not amenable to standard design libraries (e.g., memories, fuses, routing matrices and standard interconnects) with components which are describable in HDL and amenable to standard design libraries,. Embodiments of the present invention provide programmable logic blocks, which are synthesizable and do not use fuses, RAM look up tables, standard interconnect or routing matrices which are not amenable to a standards design library. One embodiment of the present invention constructs modules entirely from standard gates, which are synthesizable, fast and consume less power. The described architecture is easy to scale because the basic programmable logic block may be duplicated as many times as required.
A method for describing a user programmable logic function generator in Verilog language is disclosed. The logic function generator includes a multiplexer having a plurality of select inputs and a plurality of data inputs, which are preloaded bits. The logic function generator generates a function of the select inputs. The logic function generator receives user""s input through the plurality of data inputs to generate an output of a desired logic function of the select inputs. The logic function generator is entirely made of standard gates, which is amenable to representation by design libraries. In one embodiment, flip-flops or non-volatile cells may be used as the preloaded bits. The invention further provides a user with greater flexibility by allowing a cascading of a number of logic function generators for generating multi-variable functions generated of a greater number of select inputs.
The Verilog description can be used to generate a standard cell library, which can then be integrated into other IC designs as needed to provide a programmable logic device. Integration into well-known IC technologies is possible because the standard cell library is gates only.
More specifically, embodiments of the present invention include a memory stored Verilog description of a circuit, comprising a programmable circuit for storing a function. The programmable circuit includes a first multiplexer including: a plurality of select inputs; a plurality of first data inputs; and an output. The first multiplexer includes a plurality of programmable bits coupled to each one of the plurality of first data inputs for implementing a logic function of the select inputs. The programmable circuit further includes a plurality of latches coupled to the output of the first multiplexer, a second multiplexer including a plurality of inputs including the output of the first multiplexer and a plurality of second data inputs. The second multiplexer is logically coupled to the first multiplexer and has an output. There are a plurality of programmable bits coupled to each one of the plurality of second data inputs for receiving the output of the first multiplexer.